FPGA based hardware as a coprocessor

The process of hardware – software co-design of satellite data acquisition system is described. The hardware components are targeted to execute on a reconfigurable hardware coprocessor which communicates with a host computer that executes the software tasks. Control of the data flow between device interfaces, processing blocks and memories in a data acquisition system is complex in hardware implementation.. With growing computational needs, high design and NRE costs of ASICs, FPGA based co-processor has become a viable alternative. The main objective of our co-design methodology is the usage of hardware designing of algorithms, simulation and synthesis.